Electrostatic discharge (ESD) protection circuits safely discharge a protected pad or node in response to ESD events while allowing lower level signals during normal operation. The trigger voltage of an ESD clamp circuit is typically set above and expected maximum signal level for a protected pad during normal host circuit operation, with a certain amount of margin to prevent false triggering and to mitigate leakage. The trigger voltage of certain ESD protection clamps are triggered by voltage breakdown of a p/n-well junction. However, this breakdown level may be significantly higher than the normal signal level for a protected node, leading to insufficient protection. For example, lateral NPN bipolar transistors can be triggered by carrier injection into the base to conduct ESD event current to protect an I/O pad. In one self-biased approach, the NPN transistor is triggered by increasing the collector voltage to inject enough carriers into the substrate (base) to turn on the NPN. This high breakdown voltage is achieved by selectively masking a P-doped buried layer (PBL) near a deep N well at the expense of a PBL mask. Without the use of PBL mask, this breakdown voltage goes below the operating voltage making the cell useless.